I think I've got it figured out. Here is the schematic of the daughter board modifications.
https://drive.google.com/open?id=1UAkYJ ... lNvO0zYuVa
The motherboard piggyback is the normal one except the lead that went to the daughterboard now goes to pin 1 of U5L on motherboard which is address line A23.
The modification makes the piggyback RAM appear starting at location C00000. With the address number going as A0...A23 that address would have ones in A22 and A23 with the rest zeros.
The circuit shown basically passes the original A23, A22 states to A23M and A22M if the address is outside of the region chosen for the piggyback ram. It's like the modification isn't there. To be within that region A23=1, A22=1, A21=0, A20=0, A19=0. It will be outside if any of those values changes.
When the 68000 does a read cycle is turns on the AS* address strobe output to the DPALEN pal U5L. When the address is in the right range it turns on the RAM enable RE*. If you look at the logic equations for DPALEN the right range is when A21-A23 are all 0.
The logic equations for the PALS are here: https://drive.google.com/open?id=1FcBPo ... Y8QLi4CsXK
However A23 and A22 are 1 when we're at C00000. What the logic circuit in the mod does is supply 0 to the new A23M and A22M lines to DPALEN. Then DPALEN is able assert RE*.
A23 is 1 though so the line to the piggyback RAM is now enabled. The existing motherboard decoding does the rest.
The schematics and basic operating theory of the A1000 can be found here: http://www.devili.iki.fi/mirrors/4x4.hopto.org/
It was a very clever way to avoid having a lot of address decoding and also puts the ram in a location that won't be misinterpreted as chip ram. I'm amazed that anyone came up with the idea. I wish I knew who they were.